The embodiments of the present invention relate generally to memory architecture and associated operation. More particularly, the invention provides improved partial/full array/block erase schemes on some randomly selected full or partial memory blocks in partial/full array while the program and read operations are being concurrently executed on the other partial array in a 2D/3D NAND array based on 2-level local/global bitline (BL) hierarchical architecture.
The state-of-art 2D NAND memory and NAND-based system are not just a feasible option but already become the very popular component for desktop and laptop computers, cellular phone, data center, and/or network storage applications. The most advanced technology node for 2D NAND design is 15 nm node (1y-node) and the highest density is 128 Gb 8-state TLC per die. The further 2D NAND cell and technology scaling below 15 nm node to increase die memory density beyond 128 Gb has encountered a tremendous challenge due to reaching the technology and physical device limits. In order to increase NAND die memory density beyond 128 Gb to a level even higher than 1 Tb, the NAND industry has used 3D NAND cell technology as an alternative solution beyond the 2D NAND technology for years. Currently, both 2D and 3D NAND flash memory and system designs from SLC, MLC to TLC are coexisting but the 2D NAND captures more market share.
Although the die density improvement of 3D NAND technology looks promising in the near future, the improvements of performances and reliability of a 3D NAND design over 2D NAND counterpart are about 2 folds only and not significant. When flash technology migrates to 1×nm-node for a 2D NAND and 2×nm-node for a 3D NAND with tighter spacing between adjacent BLs and between adjacent WLs, the severe long-held AC (BL-BL switching charge/discharge-induced) coupling effect between any two physically adjacent BLs and the DC (BL-BL and WL-WL programing threshold Vt-induced) coupling effects (Yupin-effect) between any two physically adjacent BLs and WLs have resulted in highly unreliable or even failed nLC operations with more errors and less P/E cycles, particularly for the multi-level NAND Program and Read operations such as MLC, TLC, not mentioning XLC.
In addition, the advancements of NAND cell scaling also worsen HV Vpgm, MHV Vpass and LHV Vread gate disturbance or stress issues during respective nLC operations in all aspects such as program, read, program-verify and erase-verify in both 2D and 3D NAND flash memories. Note, the above HV stands for a High-Voltage (HV) of 16V˜25V for single selected programmed WL in the selected block during an nLC program operation. The above MHV stands for a Medium-High-Voltage (MHV) of about 10V for Z non-selected passing WLs in the selected NAND block during a nLC program operation, where Z=63 when a NAND string comprising of 64 cells in series with two selected transistors. Lastly, the above LHV stands for a Low-High-Voltage of 6V for Z non-selected 63 WLs in each selected NAND block as passing WLs during an nLC read operation. The degree of above three gate voltage stresses in order is that Vpgm>Vpass>Vread, while the gate stress or disturb time in order is Tread>Tpass>Tpgm. For example, Tpass=64×Tpgm in the 64-cell NAND string array, while Tread>1,000×Tpgm typically because more read than program in most of NAND applications.
In general, the averaged P/E cycle spec for SLC NAND is 100K, MLC NAND is about 10K, TLC NAND is 3K or below, while Read P/E cycle performance is not mentioned specifically in NAND product spec. But as thumb of rule, Read P/E cycle spec is about 1000 folds of each corresponding nLC P/E cycle spec. In summary, the lowest Vread has the lowest HV stress, thus the least data degradation, while the highest Vpgm has the highest HV program stress, thus the worst data degradation and P/E NAND. As a result, the Vpgm plays the dominant role in determining the final P/E cycle spec.
As a matter of fact, the total HV stresses of 2D and 3D NAND flash cells during NAND product life cycle are not only limited to above 3 said HV program and read operations. In addition, conventionally, the HV 20V (Verase) stress of NAND Erase operation is much higher than Vpgm stress because Terase is much longer than Tpgm, Terase>>Tpgm, even though Verase is set to be compatible with Vpgm, e.g., Verase=Vpgm=20V. For example, Terase>2 ms, while Tpgm of TSLC=250 μs, TMLC=750 μs, TTLC≈1-2 ms.
In other words, as TLC NAND is gradually prevailing in NAND market place in 2015 and beyond, the degree of lengthy cycle time of nLC Program and Program-Verify and Erase stresses play almost equal weight in determining the final P/E cycle spec. In addition, for a more successful TLC design, the Vpass and Vread stresses have to be also taken into the serious consideration. As a result, both in 2D and 3D NAND designs, more effective voltages and time reduction of all HV, MHV, and LHV stresses to increase not only P/E cycles but also P/E/R cycles becomes pivotal for the nLC life cycle. Note, herein E stands for erase, P stands for program, while R stands for read.
In light of above said AC and DC BL-BL and WL-WL coupling effects and HV, MHV and LHV stresses, although many techniques have been proposed and utilized conventional non-hierarchical 2D and 3D NAND designs and productions for years, these techniques cannot effectively reduce the varied HV stress time and voltages. Besides, in the conventional NAND design, only one NAND operation such as read, program and erase can be selectively performed at a time in each NAND plane, thus whole NAND memory and system performances are dramatically jeopardized.
Thereby, improved 2D/3D hierarchical NAND array architectures that allow the concurrent read, program and erase operations in any partial/full 2D/3D NAND planes with goals to effectively achieve reduction of HV stress voltage, legacies, power-consumption and numbers of error-bit of nLC read, program and erase operations are desired.